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copyright 1997 by dallas semiconductor corporation. all rights reserved. for important information regarding patents and other intellectual property rights, please refer to dallas semiconductor data books. DS1251Y 4096k nv sram with phantom clock DS1251Y 032697 1/12 features ? real time clock keeps track of hundredths of seconds, minutes, hours, days, date of the month, months, and years ? 512k x 8 nv sram directly replaces volatile static ram or eeprom ? embedded lithium energy cell maintains calendar op- eration and retains ram data ? watch function is transparent to ram operation ? month and year determine the number of days in each month; valid up to 2100 ? standard 32pin jedec pinout ? full 10% operating range ? operating temperature range 0 c to 70 c ? accuracy is better than 1 minute/month @ 25 c ? over 10 years of data retention in the absence of power ? available in 120 ns and 150 ns access time ordering information DS1251Y120 120 ns access DS1251Y150 150 ns access pin assignment 32pin encapsulated package 740 mil flush v cc a15 a17 we a13 a8 a9 a11 oe a10 ce dq7 dq6 dq5 dq4 dq3 a18/rst a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 pin description a 0 a 18 address inputs ce chip enable gnd ground dq 0 dq 7 data in/data out v cc power (+5v) we write enable oe output enable rst reset description the DS1251Y 4096k nv sram with phantom clock is a fully static nonvolatile ram (organized as 512k words by 8 bits) with a builtin real time clock. the DS1251Y has a selfcontained lithium energy source and control circuitry which constantly monitors v cc for an outof tolerance condition. when such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent garbled data in both the memory and real time clock. the phantom clock provides timekeeping information including hundredths of seconds, seconds, minutes, hours, day, date, month, and year information. the date at the end of the month is automatically adjusted for months with less than 31 days, including correction for leap years. the phantom clock operates in either 24hour or 12hour format with an am/pm indicator. .com .com .com 4 .com u datasheet
DS1251Y 032697 2/12 ram read mode the DS1251Y executes a read cycle whenever we (write enable) is inactive (high) and ce (chip enable) is active (low). the unique address specified by the 17 ad- dress inputs (a0a18) defines which of the 512k bytes of data is to be accessed. valid data will be available to the eight data output drivers within t acc (access time) after the last address input signal is stable, providing that ce and oe (output enable) access times and states are also satisfied. if oe and ce access times are not satisfied, then data access must be measured from the later occurring signal (ce or oe ) and the limiting pa- rameter is either t co for ce or t oe for oe rather than ad- dress access. ram write mode the DS1251Y is in the write mode whenever the we and ce signals are in the active (low) state after address inputs are stable. the latter occurring falling edge of ce or we will determine the start of the write cycle. the write cycle is terminated by the earlier rising edge of ce or we . all address inputs must be kept valid throughout the write cycle. we must return to the high state for a minimum recovery time (t wr ) before another cycle can be initiated. the oe control signal should be kept inac- tive (high) during write cycles to avoid bus contention. however, if the output bus has been enabled (ce and oe active) then we will disable the outputs in t odw from its falling edge. data retention mode the DS1251Y provides full functional capability for v cc greater than 4.5 volts and write protects by approxi- mately 4.0 volts. data is maintained in the absence of v cc without any additional support circuitry. the non- volatile static ram constantly monitors v cc . should the supply voltage decay, the ram automatically write pro- tects itself. all inputs to the ram become adon't careo and all outputs are high impedance. as v cc falls below approximately 3.0 volts, the power switching circuit con- nects the lithium energy source to ram to retain data. during powerup, when v cc rises above approximately 3.0 volts, the power switching circuit connects external v cc to the ram and disconnects the lithium energy source. normal ram operation can resume after v cc exceeds 4.5 volts. phantom clock operation communication with the phantom clock is established by pattern recognition on a serial bit stream of 64 bits which must be matched by executing 64 consecutive write cycles containing the proper data on dq0. all ac- cesses which occur prior to recognition of the 64bit pat- tern are directed to memory. after recognition is established, the next 64 read or write cycles either extract or update data in the phantom clock, and memory access is inhibited. data transfer to and from the timekeeping function is ac- complished with a serial bit stream under control of chip enable (ce ), output enable (oe ), and write enable (we ). initially, a read cycle to any memory location us- ing the ce and oe control of the phantom clock starts the pattern recognition sequence by moving a pointer to the first bit of the 64bit comparison register. next, 64 consecutive write cycles are executed using the ce and we control of the smartwatch. these 64 write cycles are used only to gain access to the phantom clock. therefore, any address to the memory in the socket is acceptable. however, the write cycles generated to gain access to the phantom clock are also writing data to a location in the mated ram. the preferred way to manage this requirement is to set aside just one ad- dress location in ram as a phantom clock scratch pad. when the first write cycle is executed, it is compared to bit 0 of the 64bit comparison register. if a match is found, the pointer increments to the next location of the comparison register and awaits the next write cycle. if a match is not found, the pointer does not advance and all subsequent write cycles are ignored. if a read cycle oc- curs at any time during pattern recognition, the present sequence is aborted and the comparison register point- er is reset. pattern recognition continues for a total of 64 write cycles as described above until all the bits in the comparison register have been matched (this bit pattern is shown in figure 1). with a correct match for 64bits, the phantom clock is enabled and data transfer to or from the timekeeping registers can proceed. the next 64 cycles will cause the phantom clock to either receive or transmit data on dq0, depending on the level of the oe pin or the we pin. cycles to other locations outside the memory block can be interleaved with ce cycles without interrupting the pattern recognition sequence or data transfer sequence to the phantom clock. .com .com .com .com 4 .com u datasheet
DS1251Y 032697 3/12 phantom clock register information the phantom clock information is contained in eight registers of 8bits, each of which is sequentially ac- cessed one bit at a time after the 64bit pattern recogni- tion sequence has been completed. when updating the phantom clock registers, each register must be han- dled in groups of 8bits. writing and reading individual bits within a register could produce erroneous results. these read/write registers are defined in figure 2. data contained in the phantom clock register is in binary coded decimal format (bcd). reading and writ- ing the registers is always accomplished by stepping through all eight registers, starting with bit 0 of register 0 and ending with bit 7 of register 7. phantom clock register definition figure 1 76543210 11000101 00111010 10100011 01011100 11000101 00111010 10100011 01011100 c5 3a a3 5c c5 3a a3 5c byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 hex value note: the pattern recognition in hex is c5, 3a, a3, 5c, c5, 3a, a3, 5c. the odds of this pattern being accidentally dupli- cated and causing inadvertent entry to the phantom clock is less than 1 in 10 19 . this pattern is sent to the phantom clock lsb to msb. .com .com .com .com 4 .com u datasheet
DS1251Y 032697 4/12 phantom clock register definition figure 2 7654 3210 0.1 sec 0099 0059 0059 0112 0107 0131 0112 0099 0 1 2 3 4 5 6 7 range (bcd) register 0 0 12/24 0 10 hr 00 0 00 000 10 month 10 year year 0.01 sec 0023 10 sec seconds 10 min minutes a/p hour osc rst day 10 date date month am-pm/12/24 mode bit 7 of the hours register is defined as the 12 or 24hour mode select bit. when high, the 12hour mode is selected. in the 12hour mode, bit 5 is the am/pm bit with logic high being pm. in the 24hour mode, bit 5 is the second 10-hour bit (2023 hours). oscillator and reset bits bits 4 and 5 of the day register are used to control the reset and oscillator functions. bit 4 controls the reset (pin 1). when the reset bit is set to logic 1, the reset input pin is ignored. when the reset bit is set to logic 0, a low input on the reset pin will cause the phantom clock to abort data transfer without changing data in the watch registers. bit 5 controls the oscillator. when set to logic 1, the oscillator is off. when set to log- ic 0, the oscillator turns on and the watch becomes op- erational. these bits are shipped from the factory set to a logic 1. zero bits registers 1, 2, 3, 4, 5, and 6 contain one or more bits which will always read logic 0. when writing these loca- tions, either a logic 1 or 0 is acceptable. .com .com .com .com 4 .com u datasheet
DS1251Y 032697 5/12 absolute maximum ratings* voltage on any pin relative to ground 0.3v to +7.0v operating temperature 0 c to 70 c storage temperature 40 c to +70 c soldering temperature 260 c for 10 seconds (see note 13) * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c) parameter symbol min typ max units notes power supply voltage v cc 4.5 5.0 5.5 v input logic 1 v ih 2.2 v cc +0.3 v input logic 0 v il 0.3 +0.8 v dc electrical characteristics (0 c to 70 c; v cc = 5v 10%) parameter symbol min typ max units notes input leakage current i il 1.0 +1.0 m a 12 i/o leakage current ce v ih v cc i io 1.0 +1.0 m a output current @ 2.4 volts i oh 1.0 ma output current @ 0.4 volts i ol 2.0 ma standby current ce = 2.2 volts i ccs1 5.0 10 ma standby current ce = v cc 0.5 volts i ccs2 3.0 5.0 ma operating current t cyc = 200 ns i cc01 85 ma dc test conditions outputs are open; all voltages are referenced to ground. capacitance (t a = 25 c) parameter symbol min typ max units notes input capacitance c in 5 10 pf input/output capacitance c i/o 5 10 pf .com .com .com .com 4 .com u datasheet
DS1251Y 032697 6/12 memory ac electrical characteristics (0 c to 70 c; v cc = 5.0v 10%) parameter symbol DS1251Y-120 DS1251Y-150 units notes parameter symbol min max min max units notes read cycle time t rc 120 150 ns access time t acc 120 150 ns oe to output valid t oe 60 70 ns ce to output valid t co 120 150 ns oe or ce to output active t coe 5 5 ns 5 output high z from deselection t od 40 70 ns 5 output hold from address change t oh 5 5 ns write cycle time t wc 120 150 ns write pulse width t wp 90 100 ns 3 address setup time t aw 0 0 ns write recovery time t wr 20 20 ns output high z from we t odw 40 70 ns 5 output active from we t oew 5 5 ns 5 data setup time t ds 50 60 ns 4 data hold time from we t dh 20 20 ns 4 ac test conditions output load: 50 pf + 1ttl gate input pulse levels: 03 volts timing measurement reference levels input: 1.5 volts output: 1.5 volts input pulse rise and fall times: 5 ns .com .com .com .com 4 .com u datasheet
DS1251Y 032697 7/12 phantom clock ac electrical characteristics (0 c to 70 c; v cc = 4.5 to 5.5v) parameter symbol min typ max units notes read cycle time t rc 120 ns ce access time t co 100 ns oe access time t oe 100 ns ce to output low z t coe 10 ns oe to output low z t oee 10 ns ce to output high z t od 40 ns 5 oe to output high z t odo 40 ns 5 read recovery t rr 20 ns write cycle time t wc 120 ns write pulse width t wp 100 ns write recovery t wr 20 ns 10 data setup time t ds 40 ns 11 data hold time t dh 10 ns 11 ce pulse width t cw 100 ns reset pulse width t rst 200 ns ce high to powerfail t pf 0 ns power-down/power-up timing parameter symbol min typ max units notes ce at v ih before powerdown t pd 0 m s v cc slew from 4.5v to 0 volts (ce at v ih ) t f 300 m s v cc slew from 0v to 4.5 volts (ce at v ih ) t r 0 m s ce at v ih after powerup t rec 2 ms (t a = 25 c) parameter symbol min typ max units notes expected data retention time t dr 10 years 9 warning: under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery backup mode. .com .com .com .com 4 .com u datasheet
DS1251Y 032697 8/12 memory read cycle (note 1) ?????? ?????? ??????? ??????? ??? ??? ??? ??? t rc t acc t co t oe t coe t coe t oh t od t od output data valid v il v ih v il v ih v il v ih v ih v il v ih v ih v ih v il v ol v oh v ol v oh addresses ce oe d out memory write cycle 1 (notes 2, 6, and 7) ????????? ????????? t wc t wr v il v ih v il v ih v il v ih v il ce ???? ???? v il v il v ih v il v ih data in stable t wp t odw t oew t dh t ds we address dq0dq7 t aw v ih v ih high impedance .com .com .com .com 4 .com u datasheet
DS1251Y 032697 9/12 memory write cycle 2 (notes 2 and 8) ????????? ????????? t wc v il v ih v il v ih v il v ih v il ce ???? ???? v il v il v ih v il v ih data in stable t wp t coe t oew t dh t ds we addresses dq0dq7 t aw v ih v ih t wr v il v il t odw we = v ih reset for phantom clock rst t rst read cycle to phantom clock output data valid t rc t co t rr t od t oe t odo t coe t oee ce oe q .com .com .com .com 4 .com u datasheet
DS1251Y 032697 10/12 write cycle to phantom clock data in stable t wc t wp t wr t cw t wr t ds t dh t dh we ce d oe = v ih power-down/power-up condition data retention time t dr leakage current i l supplied from lithium cell t r t rec t pd t f v cc 4.50v 3.2v ce .com .com .com .com 4 .com u datasheet
DS1251Y 032697 11/12 notes: 1. we is high for a read cycle. 2. oe = v ih or v il . if oe = v ih during write cycle, the output buffers remain in a high impedance state. 3. t wp is specified as the logical and of ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t dh , t ds are measured from the earlier of ce or we going high. 5. these parameters are sampled with a 50 pf load and are not 100% tested. 6. if the ce low transition occurs simultaneously with or later than the we low transition in write cycle 1, the output buffers remain in a high impedance state during this period. 7. if the ce high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in a high impedance state during this period. 8. if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output buffers remain in a high impedance state during this period. 9. the expected t dr is defined as accumulative time in the absence of v cc with the clock oscillator running. 10. t wr is a function of the latter occurring edge of we or ce . 11. t dh and t ds are a function of the first occurring edge of we or ce . 12. rst (pin1) has an internal pullup resistor. 13. realtime clock modules can be successfully processed through conventional wavesoldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85 c. post solder cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used. .com .com .com .com 4 .com u datasheet
DS1251Y 032697 12/12 DS1251Y 4096k nv sram with phantom clock a 1 c f g k d h b e j dim 32pin min pkg max a in. 1.720 1.740 mm 43.69 44.20 b in. 0.720 0.740 mm 18.29 18.80 c in. 0.395 0.415 mm 10.03 10.54 d in. 0.090 0.120 mm 2.29 3.05 e in. 0.017 0.030 mm 0.43 0.76 f in. 0.120 0.160 mm 3.05 4.06 g in. 0.090 0.110 mm 2.29 2.79 h in. 0.590 0.630 mm 14.99 16.00 j in. 0.008 0.012 mm 0.20 0.30 k in. 0.015 0.021 mm 0.38 0.53 .com .com .com 4 .com u datasheet

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